p p j q190 2 september 30,2015 - rev.00 page 1 3 0 v n - c hannel enhancement mode mosfet C esd protected voltage 3 0 v current 50 0m a dfn3l unit: inch(mm) f eatures ? r ds(on) , v gs @ 4.5 v , i d @ 350m a< 1.2 ? ? r ds(on) , v gs @ 2 .5 v , i d @ 200m a< 1.6 ? ? r ds(on) , v gs @ 1.8 v , i d @ 8 0ma < 2. 3 ? ? r ds(on) , v gs @ 1.5 v , i d @ 10ma < 2.5 ? ? specially designed for switch load, pwm application, etc. ? esd protected 2kv hbm ? lead free in compliance with eu rohs 2011/65/eu directive ? green molding compound as per iec61249 std. (halogen free) mechanical data ? case: dfn3l package ? terminals : solderable per mil - std - 750, method 2026 ? approx. weight: 0.00004 ounces, 0 .0011 grams ? marking: 2 parameter symbol limit units drain - source voltage v ds 30 v gate - source voltage v gs + 10 v continuous drain current i d 50 0 ma pulsed drain current i dm 15 00 ma power dissipation t a =25 o c p d 7 0 0 m w derate above 25 o c 5.6 m w/ o c operatin g junction an d storage temperature range t j ,t stg - 55~150 o c typical thermal resistance - j unction to ambient (note 3 ) r ja 175 o c /w maximum ratings and thermal characteristics (t a =25 o c unless otherwise noted)
p p j q190 2 september 30,2015 - rev.00 page 2 e lectrical c haracteristics (t a =25 o c unless otherwise noted) parameter symbol test condition min. typ. max. units static drain - source breakdown voltage bv dss v gs = 0 v, i d = 25 0ua 3 0 - - v gate threshold voltage v gs(th) v ds =v gs , i d = 250 ua 0.6 0.85 1.1 v drain - source on - state resistance r ds(on) v gs = 4.5 v, i d = 350m a - 0.94 1.2 gs = 2.5 v, i d = 200m a - 1.32 1.6 v gs = 1.8 v, i d = 8 0m a - 1.82 2. 3 v gs = 1.5 v, i d = 10m a - 2. 5 - zero gate voltage drain current i dss v ds = 30 v, v gs =0v - 0.01 1 u a gate - source leakage current i gss v gs = + 8 v, v ds =0v - - + 10 v gs = + 5 v, v ds =0v - - + 1 dynamic (note 5 ) total gate charge q g v ds = 15 v, i d = 350m a, v gs = 4.5v (note 1 , 2 ) - 0.87 - nc gate - source charge q gs - 0.26 - gate - drain charge q gd - 0.16 - input capacitance ciss v ds = 15 v, v gs = 0 v, f=1.0mhz - 34 - pf output capacitance coss - 8.9 - reverse transfer capacitance crss - 2.5 - turn - on delay time t d (on) v dd = 15 v, i d =80m a, v g s = 4.0v, r g = 6 (note 1 , 2 ) - 7.1 - ns turn - on rise time tr - 20 - turn - o ff delay time t d (off) - 41 - turn - o ff fall time tf - 31 - drain - source diode maximum continuous drain - source diode forward current i s --- - - 350 m a diode forward voltage v sd i s = 350m a, v gs = 0 v - 0.88 1.3 v notes : 1. pulse width < 300us, duty cycle < 2% 2. essentially independent of operating temperature typical characteristics . 3. r ? ja is the sum of the junction - to - case and case - to - ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins m ounted on a 1 inch fr - 4 with 2oz . square pad of copper 4. the maximum current rating is packag e limited 5. guaranteed by design, not subject to product ion testing.
p p j q190 2 september 30,2015 - rev.00 page 3 t ypical characteristic curves fig.1 on - region characteristics fig. 2 transfer characteristics fig. 3 on - resistance vs. drain current fig. 4 on - resistance vs. junction temperature fig. 5 on - resistance variation with vgs. fig. 6 body d i ode characteristics
p p j q190 2 september 30,2015 - rev.00 page 4 t ypical characteristic curves fig. 7 gate - charge characteristics fig. 8 threshold voltage variation with temperature . fig. 9 capacitance vs. drain - source voltage.
p p j q190 2 september 30,2015 - rev.00 page 5 part no packing code version mounting pad layout part no packing code package type packing type marking ver sion PJQ1902 _r1_000 01 dfn3l 8k pcs / 7
p p j q190 2 september 30,2015 - rev.00 page 6 disclaimer
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